Developments in the semiconductor industry over the years have focused on a wide array of technical disciplines, device designs, and device packaging approaches in order to achieve improved semiconductor performance. Although many improvements have been obtained through device miniaturization, other improvements have resulted from creating multifunction devices on one semiconductor die. Such multi-function devices may have transistors that have different performance objectives that may be achieved through different physical characteristics of the transistors of the devices.
Triple gate oxide techniques may be used to improve characteristics of semiconductor devices in a chip that includes high-performance transistors with thin gate oxide layers, low power devices with thicker gate oxide layers, and high voltage input/output ports.
Forming more than two oxide layers having differing thicknesses conventionally utilizes a method where oxide layers are partially removed before forming other oxide layers. Then, additional oxide layers are deposited on the gate predetermined region from which the oxide layers have been partially removed. Photolithography can be used to remove oxide layers. However, this may result in reduced transistor performance and increased leakage current.
A method of fabricating a plurality of gate oxide layers without performing the photolithographic etching process is disclosed in U.S. Pat. No. 6,147,008 entitled “CREATION OF MULTIPLE GATE OXIDE WITH HIGH THICKNESS RATIO IN FLASH MEMORY PROCESS” by Siow Lee Chwa et al.
FIG. 1 to FIG. 3 are cross-sectional views of such a conventional method of fabricating triple gate oxide layers. Region A illustrates a part of the semiconductor substrate including high-performance transistors, region B illustrates a part of the substrate including low power transistors, and region C illustrates a part of the substrate including input/output devices.
Referring to FIG. 1, a plurality of active regions are defined by forming an isolation layer 12 on a semiconductor substrate 10. As a matter of convenience, active regions of region A are defined as a first active region 20, active regions of region B are defined as a second active region 22, and active regions of region C are defined as a third active region 24. As shown in FIG. 1, a first oxide layer 14 is formed on the semiconductor substrate that includes the isolation layer 12.
Referring to FIG. 2, a photoresist layer is formed on the entire semiconductor substrate 10 including the first oxide layer 14. The photoresist layer is patterned to form a photoresist pattern 16 exposing the first active region 20. Nitrogen ions are then implanted into the semiconductor substrate 10 to form an oxidation barrier layer 18, using the photoresist pattern 16 as an ion implantation mask.
Referring to FIG. 3, the photoresist pattern 16 is removed. The first oxide layer 14 is also removed from the first active region 20 and the second active region 22. A second oxide layer is formed on the entire semiconductor substrate 10. As a result, a first gate oxide layer 32 and a second gate oxide layer 30 are respectively formed on the first active region 20 and the second active region 22. However, the oxidation barrier layer 18 suppresses oxidation of the first active region 20. Thus, the thickness of the first gate oxide layer 32 is thinner than that of the second gate oxide layer 30. The thickness of the second gate oxide layer 30 is the same as that of the second oxide layer formed on the semiconductor substrate. A third gate oxide layer 14A is formed on the third active region 24, and is composed of a combination of the first oxide layer and the second oxide layer.
Accordingly, in methods of fabricating triple gate oxide layers according to the prior art, a thinner oxide layer may be formed by implanting nitrogen in active regions. As such, a semiconductor device including gate oxide layers of different thicknesses may be formed. However, implanting nitrogen ions into the substrate may cause crystalline damage. When crystalline damage overlaps with the transistor junctions, transistor leakage current may be increased. In particular, leakage current may be increased at PMOS transistor junctions positioned on an edge of the active regions. Moreover, it may be difficult to control the thickness of the oxide layers when using nitrogen ion implantation.